1. Field of Invention
Various embodiments of the present invention relate to a semiconductor design technology and, more particularly, to an erase operation of a semiconductor device.
2. Description of Related Art
A semiconductor memory device, for example, a NAND flash memory, includes a memory cell array in which data are stored. The memory cell array includes a plurality of cell blocks. When program, erase and read operations are performed, a cell block may be selected from among the plurality of cell blocks included in the memory cell array, and corresponding operations may be performed on the selected cell block.
During an erase operation, 0V may be applied to word lines coupled to memory cells within a selected cell block, or the word lines may be floated while an erase voltage may be applied to a bulk of the selected cell block. The bulk is a region where a well within a substrate including the cell blocks is formed.
Recently, an erase operation is performed using an incremental step pulse erase (ISPE) method to reduce width of threshold voltage distributions of memory cells being erased. An erase operation using the ISPE method may be performed by repeating a plurality of erase loops.
An erase loop may include an operation of reducing threshold voltages of memory cells by applying an erase voltage to a bulk and an erase verify operation being carried out as to whether or not the threshold voltages of the memory cells in a selected cell block are reduced to a target level. During the erase verify operation, the target level may be determined depending on an erase verify voltage being applied to all of word lines coupled to the selected cell block. In general, in terms of the erase verify voltage, a voltage having a fixed level may be used.
As a result of the erase verify operation, if it is determined that there are memory cells having threshold voltages not reduced to the target level, the erase loop may be repeated until the threshold voltages of all the memory cells in the selected cell block are reduced to the target level while the erase voltage being applied to the bulk is gradually increased. The erase operation is completed when the threshold voltages of all of the memory cells in the selected cell block are reduced to the target level.
However, as an erase-program cycling number increases, the semiconductor memory device may be physically degraded due to physical properties thereof, and electrical characteristics of the semiconductor memory device may also be degraded. The erase-program cycling number refers to how many times a pair of a program operation and an erase operation is performed. In other words, a single set of program and erase operations may refer to a single erase-program cycling. As the erase-program cycling number increases, erase disturbance of memory cells may be more likely to occur. As a result, it may be more difficult to reduce threshold voltages of the memory cells to a target erase level during an erase operation, and an erase voltage with a higher voltage level may be required to reduce the threshold voltages of the memory cells to the target erase level. In addition, as the time taken to reduce the threshold voltages to the target erase level increases, stress on the semiconductor memory device may also increase.